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lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 1 of 12 preliminary datasheet lp 630 4b buck 2a, 4 - channel power management ic general description the LP6304B is a 2a buck converter of 4 - ch power management ic for applications powered by one li - ion battery or a dc 5v adapter. it integrates four synchronous buck converters and can provide high efficiency output at light load and heavy load operation. the internal compensation architectur e simplifies the application circuit design. besides, the independent enable control makes the designer have the greatest flexibility to optimize timing for power sequencing purposes. the LP6304B is available in a 24 pin t qfn 4x4 package. order inform ation lp 630 4b f: pb /h alogen - free package type qv : tqfn 4 4 applications ? smart phone ? ip camera ? ott ? digital camera features ? 2. 2 v to 5.5v input voltage range ? four buck converters ? output voltage range: 0.6v to vin ? continuous loading: ? 2a (buck1), 2 a (buck2), 2a (buck3), 2 a (buck4) ? fixed 1.5mhz switching frequency ? 100% duty cycle low dropout operation ? <1ua shutdown current ? independent enable control ? internal compensation ? cycle - by - cycle current limit ? short circuit protection ? auto recovery otp protection ? available in 24 - pin 4mm x 4mm qfn package marking information device marking package shipping LP6304B lps LP6304B xxx tqfn4x4 3k/reel note: x is series number.
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 2 of 12 preliminary datasheet lp 630 4b functional pin description package type pin configurations t q fn 4 4 pin description pin name description 1 gnd 3 power common ground . 2 fb 3 ch3 feedback reference voltage pin . 3,4,15,16 nc no connecter. 5 fb 2 ch2 feedback reference voltage pin . 6 gnd 2 power common ground . 7 sw 2 ch2 switch pin . 8 v in2 ch2 supply input power . 9 en 2 ch2 chip enable . 10 en 1 ch1 chip enable . 11 v in1 ch1 supply input power . 12 sw 1 ch1 switch pin . 13 gnd 1 power common ground . 14 fb 1 ch1 feedback reference voltage pin . 17 fb 4 ch4 feedback reference voltage pin . 18 gnd 4 power common ground . 19 sw 4 ch4 switch pin . 20 v in4 ch4 supply input power . 21 en 4 ch4 chip enable . 22 en 3 ch3 chip enable . 23 v in3 ch3 supply input power . 24 sw 3 ch3 switch pin . g n d 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 t o p v i e w f b 1 n c n c f b 4 g n d 4 l x 2 v i n 2 e n 2 e n 1 v i n 1 l x 1 l x 4 v i n 4 e n 4 e n 3 v i n 3 l x 3 g n d 2 f b 2 n c n c f b 3 g n d 3
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 3 of 12 preliminary datasheet lp 630 4b function diagram b u c k c o n v e r t e r 1 b u c k c o n v e r t e r 2 b u c k c o n v e r t e r 3 b u c k c o n v e r t e r 4 v i n 1 l x 1 g n d 1 v i n 2 l x 2 g n d 2 v i n 3 l x 3 g n d 3 v i n 4 l x 4 g n d 4 e n 4 e n 3 e n 2 e n 1 f b 4 f b 3 f b 2 f b 1
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 4 of 12 preliminary datasheet lp 630 4b application circuit l x 1 f b 1 l x 2 f b 2 l x 3 f b 3 l x 4 f b 4 v i n 1 v i n 2 v i n 3 v i n 4 e n 1 e n 2 e n 3 e n 4 g n d 1 g n d 2 g n d 3 g n d 4 v i n 5 v c 1 1 0 f c 2 1 0 f c 3 1 0 f c 4 1 0 f c 6 2 2 f c 7 2 2 f c 8 2 2 f c 9 2 2 f c 1 0 o p t i o n a l c 1 1 o p t i o n a l c 1 2 o p t i o n a l c 1 3 o p t i o n a l l 1 2 . 2 h l 2 2 . 2 h l 3 2 . 2 h l 4 2 . 2 h r 1 1 0 0 k r 2 1 0 0 k r 3 1 0 0 k r 4 1 0 0 k r 5 2 0 0 k r 6 1 0 0 k r 7 4 5 3 k r 8 1 0 0 k v o u t 4 3 . 3 v / 2 a v o u t 3 1 . 8 v / 2 a v o u t 2 1 . 2 v / 2 a v o u t 1 1 . 2 v / 2 a o n o n o n o n o f f o f f o f f o f f
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 5 of 12 preliminary datasheet lp 630 4b absolute maximum ratings note 1 ? input to gnd (vin) -------------------------------- -------------------------------- ------------------------------ - 0.3v to 6v ? o ther pin to gnd -------------------------------- -------------------------------- ----------------------------- - 0.3v to 6 v ? maximum junction temperature -------------------------------- -------------------------------- ------------------ 125c ? operating junction temperature range (t j ) -------------------------------- ------------------------ - 40 to 85 c ? storage temperature range (t j ) -------------------------------- -------------------------------- ----- - 65 to 150 ? maximum soldering temperature (at leads, 10 sec) -------------------------------- ------------------------ 260c note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operation al sections of the specifications is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. thermal information ? maximum power dissipation (p d ,t a =25 ) -------------------------------- -------------------------------- ------ 2.5 w ? thermal resistance ( ja ) -------------------------------- -------------------------------- -------------------------- 5 0 /w esd susceptibility ? hbm(human body mode) -------------------------------- -------------------------------- ----------------------------- 2kv ? mm(machine mode) -------------------------------- -------------------------------- -------------------------------- --- 200v
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 6 of 12 preliminary datasheet lp 630 4b electrical characteristics ( v inx = 5 v, t a =25c, unless otherwise noted ) parameter symbol test conditions min typ max units in put supply voltage in put voltage v in x 2.2 5.5 v control circuit input voltage v cc 2.2 5.5 v buck converter shutdown supply current i sd v en = 0v 0.1 1 a quiescent current i q v en = 2 v, no load 280 a uvlo threshold v uvlo v in rising 2 v uvlo hysteresis v uv - hys 0.1 v output load current i load 2 a reference voltage v ref 0.588 0.6 0.612 v switching frequency f sw i load = 100ma 1 1.5 2 mhz pmos current limit i lim - p 3 a pmos on - resistance note r ds(on) - p i load = 100ma 100 m nmos on - resistance note r ds(on) - n i load = 100ma 90 m enable pin input low voltage v en - l 0.4 v enable pin input high voltage v en - h 1.5 v enable input current i en 2 ua output voltage soft start t ss (0% 90%)v out 450 us over - temperature shutdown threshold t sd 150 maximum duty cycle d max 100 % note : mosfet on - resistance specifications are guaranteed by correlation to wafer level measurements.
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 7 of 12 preliminary datasheet lp 630 4b typical operating characteristics lx waveform @v out =3.3v, io=0a lx waveform @v out =3.3v, io=2a lx waveform @v out =1.1v, io=0a lx waveform @v out =1.1v, io=2a lx waveform @v out =3.3v, short output v out lx v out lx v out lx v out lx v out lx
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 8 of 12 preliminary datasheet lp 630 4b lx waveform @v out =3.3v, no load to short output lx waveform @v out =3.3v, short output to no load output waveform @v out =3.3v, io=10ma to 1a output waveform @v out =3.3v, io=100ma to 1a v out lx v out lx v out lx v out lx
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 9 of 12 preliminary datasheet lp 630 4b functional description pfm/pwm operation each of the buck regulators can be operated at pfm/pwm mode. if the output current is less than 170ma (v out =1.2v), the regulators automatically enters the pfm mode. the output voltages and output ripples at pfm mode are high er than the output voltages and output ripples at pwm mode. but at very light load, the pfm mode operation provides higher efficiency than pwm mode operation. enable control the LP6304B is a high efficiency power management ic which is designed for ipc an d ott applications. it incorporates four 2a synchronous buck regulators and can be controlled by individual en pins. the start - up time for each channel can be programmed by using the circuit shown as below: over current protection the LP6304B internal four regulators have their own cycle - by - cycle current limit circuits. when the inductor peak current exceeds the current limit threshold, the output voltage starts to drop until fb pin voltage is below the threshold. ther mal shutdown the LP6304B will automatically disabled if the die temperature is higher than the thermal shutdown threshold point. to avoid unstable operation, the hysteresi s of thermal shutdown is about 2 0 c. v i n e n g n d 1 0 0 k 1 0 n f ~ 1 0 0 n f v i n 5 v
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 10 of 12 preliminary datasheet lp 630 4b application information output voltage setting each of the regulators output voltage can be set via a resistor divider (ex. r1, r2). the output voltage is calculated by following equation: the following table lists common output voltage and the corresponding r1, r2 resistance value for reference. v out r1 r2 tolerance 3.3v 510k ? i l . large ? i l will cause larger output voltage ripple and loss, but the user can use a smaller inductor to save cost and space. on the contrary, the larger inductance can get smaller ? i l and thus the smaller output voltage ripple and loss. but it will increase the space and the cost. the inductor value can be calculated as: for most applications, 1.0uh to 2.2uh inductors are suitable for lp 6304b power dissipation the total output power dissipation of lp 6304b should not to exceed the maximum 10w range. the total output power dissipation can be calculated as: ? ? ? out1 r1 v 0.6 0.6 v r2 l x 1 f b 1 g n d l 1 1 . 5 h c 1 0 ( o p t i o n a l ) v o u t 1 1 . 1 v r 1 6 8 k r 2 8 2 k pwr out out l sw pwr v v v l i f v ? ?? ? ? ? ? ? ? ? ? ? ? ? d total out1 out1 out2 out2 out3 out3 out4 out4 p v i v i v i v i
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 11 of 12 preliminary datasheet lp 630 4b pcb layout layout is very critical for pmic designs. for lp 6304b pcb layout considerations , please refer to the following suggestions to get best performance. ? it is suggested to use 4 - layer pcb layout and place lx plane and output plane on the top layer, place vin plane in the inner layer. ? the top layer smd input and output capacitors ground plane should be connected to the internal ground layer and bottom ground plane individually by using vias. ? the gnd should be connected to inner ground layer directly by using v ia. ? high current path traces need to be widened. ? place the input capacitors as close as possible to the vin x pin to reduce noise interference. ? keep the feedback path (from v outx to fbx) away from the noise node (ex. lxx). lxx is a high current noise node. complete the layout by using short and wide traces. ? the top layer exposed pad ground plane should be connected to the internal ground layer and bottom ground plane by using a nu mber of vias to improve thermal performance. ? place the input capacitors as close as possible to the vinx pin to reduce noise interference.
lp 630 4b - 0 1 may . - 201 3 email: marketing@lowpowersemi.com www.lowpowersemi.com page 12 of 12 preliminary datasheet lp 630 4b packaging information top view recommended layout pattern bottom view side view symbol dimension dimension min. max. symbol typ. a 0.18 0.30 m 2.60 c 0.45 0.55 n 2.60 d 3.95 4.05 o 0.30 e 3.95 4.05 p 0.80 d1 2.30 2.70 q 0.50 e1 2.30 2.70 r 4.70 l 035 0.45 s 4.70 h 0.80 1.00 h1 0.17 0.25 h2 0.00 0.05

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